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| 10 | <h1>enc28j60.h</h1><a href="enc28j60_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment">00001 <span class="comment">/*! \file enc28j60.h \brief Microchip ENC28J60 Ethernet Interface Driver. */</span> |
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| 11 | 00002 <span class="comment">//*****************************************************************************</span> |
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| 12 | 00003 <span class="comment">//</span> |
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| 13 | 00004 <span class="comment">// File Name : 'enc28j60.h'</span> |
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| 14 | 00005 <span class="comment">// Title : Microchip ENC28J60 Ethernet Interface Driver</span> |
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| 15 | 00006 <span class="comment">// Author : Pascal Stang (c)2005</span> |
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| 16 | 00007 <span class="comment">// Created : 9/22/2005</span> |
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| 17 | 00008 <span class="comment">// Revised : 9/22/2005</span> |
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| 18 | 00009 <span class="comment">// Version : 0.1</span> |
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| 19 | 00010 <span class="comment">// Target MCU : Atmel AVR series</span> |
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| 20 | 00011 <span class="comment">// Editor Tabs : 4</span> |
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| 21 | 00012 <span class="comment">//</span><span class="comment"></span> |
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| 22 | 00013 <span class="comment">/// \ingroup network</span> |
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| 23 | 00014 <span class="comment">/// \defgroup enc28j60 Microchip ENC28J60 Ethernet Interface Driver (enc28j60.c)</span> |
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| 24 | 00015 <span class="comment">/// \code #include "net/enc28j60.h" \endcode</span> |
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| 25 | 00016 <span class="comment">/// \par Overview</span> |
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| 26 | 00017 <span class="comment">/// This driver provides initialization and transmit/receive</span> |
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| 27 | 00018 <span class="comment">/// functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY.</span> |
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| 28 | 00019 <span class="comment">/// This chip is novel in that it is a full MAC+PHY interface all in a 28-pin</span> |
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| 29 | 00020 <span class="comment">/// chip, using an SPI interface to the host processor.</span> |
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| 30 | 00021 <span class="comment">///</span> |
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| 31 | 00022 <span class="comment"></span><span class="comment">//</span> |
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| 32 | 00023 <span class="comment">//*****************************************************************************</span><span class="comment"></span> |
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| 33 | 00024 <span class="comment">//@{</span> |
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| 34 | 00025 <span class="comment"></span> |
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| 35 | 00026 <span class="preprocessor">#ifndef ENC28J60_H</span> |
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| 36 | 00027 <span class="preprocessor"></span><span class="preprocessor">#define ENC28J60_H</span> |
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| 37 | 00028 <span class="preprocessor"></span> |
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| 38 | 00029 <span class="preprocessor">#include "<a class="code" href="global_8h.html">global.h</a>"</span> |
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| 39 | 00030 |
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| 40 | 00031 <span class="preprocessor">#define nop() asm volatile ("nop")</span> |
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| 41 | 00032 <span class="preprocessor"></span> |
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| 42 | 00033 <span class="comment">// ENC28J60 Control Registers</span> |
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| 43 | 00034 <span class="comment">// Control register definitions are a combination of address,</span> |
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| 44 | 00035 <span class="comment">// bank number, and Ethernet/MAC/PHY indicator bits.</span> |
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| 45 | 00036 <span class="comment">// - Register address (bits 0-4)</span> |
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| 46 | 00037 <span class="comment">// - Bank number (bits 5-6)</span> |
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| 47 | 00038 <span class="comment">// - MAC/PHY indicator (bit 7)</span> |
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| 48 | 00039 <span class="preprocessor">#define ADDR_MASK 0x1F</span> |
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| 49 | 00040 <span class="preprocessor"></span><span class="preprocessor">#define BANK_MASK 0x60</span> |
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| 50 | 00041 <span class="preprocessor"></span><span class="preprocessor">#define SPRD_MASK 0x80</span> |
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| 51 | 00042 <span class="preprocessor"></span><span class="comment">// All-bank registers</span> |
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| 52 | 00043 <span class="preprocessor">#define EIE 0x1B</span> |
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| 53 | 00044 <span class="preprocessor"></span><span class="preprocessor">#define EIR 0x1C</span> |
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| 54 | 00045 <span class="preprocessor"></span><span class="preprocessor">#define ESTAT 0x1D</span> |
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| 55 | 00046 <span class="preprocessor"></span><span class="preprocessor">#define ECON2 0x1E</span> |
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| 56 | 00047 <span class="preprocessor"></span><span class="preprocessor">#define ECON1 0x1F</span> |
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| 57 | 00048 <span class="preprocessor"></span><span class="comment">// Bank 0 registers</span> |
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| 58 | 00049 <span class="preprocessor">#define ERDPTL (0x00|0x00)</span> |
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| 59 | 00050 <span class="preprocessor"></span><span class="preprocessor">#define ERDPTH (0x01|0x00)</span> |
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| 60 | 00051 <span class="preprocessor"></span><span class="preprocessor">#define EWRPTL (0x02|0x00)</span> |
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| 61 | 00052 <span class="preprocessor"></span><span class="preprocessor">#define EWRPTH (0x03|0x00)</span> |
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| 62 | 00053 <span class="preprocessor"></span><span class="preprocessor">#define ETXSTL (0x04|0x00)</span> |
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| 63 | 00054 <span class="preprocessor"></span><span class="preprocessor">#define ETXSTH (0x05|0x00)</span> |
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| 64 | 00055 <span class="preprocessor"></span><span class="preprocessor">#define ETXNDL (0x06|0x00)</span> |
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| 65 | 00056 <span class="preprocessor"></span><span class="preprocessor">#define ETXNDH (0x07|0x00)</span> |
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| 66 | 00057 <span class="preprocessor"></span><span class="preprocessor">#define ERXSTL (0x08|0x00)</span> |
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| 67 | 00058 <span class="preprocessor"></span><span class="preprocessor">#define ERXSTH (0x09|0x00)</span> |
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| 68 | 00059 <span class="preprocessor"></span><span class="preprocessor">#define ERXNDL (0x0A|0x00)</span> |
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| 69 | 00060 <span class="preprocessor"></span><span class="preprocessor">#define ERXNDH (0x0B|0x00)</span> |
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| 70 | 00061 <span class="preprocessor"></span><span class="preprocessor">#define ERXRDPTL (0x0C|0x00)</span> |
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| 71 | 00062 <span class="preprocessor"></span><span class="preprocessor">#define ERXRDPTH (0x0D|0x00)</span> |
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| 72 | 00063 <span class="preprocessor"></span><span class="preprocessor">#define ERXWRPTL (0x0E|0x00)</span> |
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| 73 | 00064 <span class="preprocessor"></span><span class="preprocessor">#define ERXWRPTH (0x0F|0x00)</span> |
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| 74 | 00065 <span class="preprocessor"></span><span class="preprocessor">#define EDMASTL (0x10|0x00)</span> |
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| 75 | 00066 <span class="preprocessor"></span><span class="preprocessor">#define EDMASTH (0x11|0x00)</span> |
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| 76 | 00067 <span class="preprocessor"></span><span class="preprocessor">#define EDMANDL (0x12|0x00)</span> |
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| 77 | 00068 <span class="preprocessor"></span><span class="preprocessor">#define EDMANDH (0x13|0x00)</span> |
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| 78 | 00069 <span class="preprocessor"></span><span class="preprocessor">#define EDMADSTL (0x14|0x00)</span> |
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| 79 | 00070 <span class="preprocessor"></span><span class="preprocessor">#define EDMADSTH (0x15|0x00)</span> |
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| 80 | 00071 <span class="preprocessor"></span><span class="preprocessor">#define EDMACSL (0x16|0x00)</span> |
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| 81 | 00072 <span class="preprocessor"></span><span class="preprocessor">#define EDMACSH (0x17|0x00)</span> |
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| 82 | 00073 <span class="preprocessor"></span><span class="comment">// Bank 1 registers</span> |
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| 83 | 00074 <span class="preprocessor">#define EHT0 (0x00|0x20)</span> |
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| 84 | 00075 <span class="preprocessor"></span><span class="preprocessor">#define EHT1 (0x01|0x20)</span> |
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| 85 | 00076 <span class="preprocessor"></span><span class="preprocessor">#define EHT2 (0x02|0x20)</span> |
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| 86 | 00077 <span class="preprocessor"></span><span class="preprocessor">#define EHT3 (0x03|0x20)</span> |
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| 87 | 00078 <span class="preprocessor"></span><span class="preprocessor">#define EHT4 (0x04|0x20)</span> |
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| 88 | 00079 <span class="preprocessor"></span><span class="preprocessor">#define EHT5 (0x05|0x20)</span> |
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| 89 | 00080 <span class="preprocessor"></span><span class="preprocessor">#define EHT6 (0x06|0x20)</span> |
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| 90 | 00081 <span class="preprocessor"></span><span class="preprocessor">#define EHT7 (0x07|0x20)</span> |
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| 91 | 00082 <span class="preprocessor"></span><span class="preprocessor">#define EPMM0 (0x08|0x20)</span> |
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| 92 | 00083 <span class="preprocessor"></span><span class="preprocessor">#define EPMM1 (0x09|0x20)</span> |
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| 93 | 00084 <span class="preprocessor"></span><span class="preprocessor">#define EPMM2 (0x0A|0x20)</span> |
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| 94 | 00085 <span class="preprocessor"></span><span class="preprocessor">#define EPMM3 (0x0B|0x20)</span> |
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| 95 | 00086 <span class="preprocessor"></span><span class="preprocessor">#define EPMM4 (0x0C|0x20)</span> |
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| 96 | 00087 <span class="preprocessor"></span><span class="preprocessor">#define EPMM5 (0x0D|0x20)</span> |
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| 97 | 00088 <span class="preprocessor"></span><span class="preprocessor">#define EPMM6 (0x0E|0x20)</span> |
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| 98 | 00089 <span class="preprocessor"></span><span class="preprocessor">#define EPMM7 (0x0F|0x20)</span> |
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| 99 | 00090 <span class="preprocessor"></span><span class="preprocessor">#define EPMCSL (0x10|0x20)</span> |
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| 100 | 00091 <span class="preprocessor"></span><span class="preprocessor">#define EPMCSH (0x11|0x20)</span> |
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| 101 | 00092 <span class="preprocessor"></span><span class="preprocessor">#define EPMOL (0x14|0x20)</span> |
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| 102 | 00093 <span class="preprocessor"></span><span class="preprocessor">#define EPMOH (0x15|0x20)</span> |
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| 103 | 00094 <span class="preprocessor"></span><span class="preprocessor">#define EWOLIE (0x16|0x20)</span> |
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| 104 | 00095 <span class="preprocessor"></span><span class="preprocessor">#define EWOLIR (0x17|0x20)</span> |
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| 105 | 00096 <span class="preprocessor"></span><span class="preprocessor">#define ERXFCON (0x18|0x20)</span> |
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| 106 | 00097 <span class="preprocessor"></span><span class="preprocessor">#define EPKTCNT (0x19|0x20)</span> |
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| 107 | 00098 <span class="preprocessor"></span><span class="comment">// Bank 2 registers</span> |
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| 108 | 00099 <span class="preprocessor">#define MACON1 (0x00|0x40|0x80)</span> |
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| 109 | 00100 <span class="preprocessor"></span><span class="preprocessor">#define MACON2 (0x01|0x40|0x80)</span> |
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| 110 | 00101 <span class="preprocessor"></span><span class="preprocessor">#define MACON3 (0x02|0x40|0x80)</span> |
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| 111 | 00102 <span class="preprocessor"></span><span class="preprocessor">#define MACON4 (0x03|0x40|0x80)</span> |
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| 112 | 00103 <span class="preprocessor"></span><span class="preprocessor">#define MABBIPG (0x04|0x40|0x80)</span> |
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| 113 | 00104 <span class="preprocessor"></span><span class="preprocessor">#define MAIPGL (0x06|0x40|0x80)</span> |
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| 114 | 00105 <span class="preprocessor"></span><span class="preprocessor">#define MAIPGH (0x07|0x40|0x80)</span> |
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| 115 | 00106 <span class="preprocessor"></span><span class="preprocessor">#define MACLCON1 (0x08|0x40|0x80)</span> |
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| 116 | 00107 <span class="preprocessor"></span><span class="preprocessor">#define MACLCON2 (0x09|0x40|0x80)</span> |
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| 117 | 00108 <span class="preprocessor"></span><span class="preprocessor">#define MAMXFLL (0x0A|0x40|0x80)</span> |
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| 118 | 00109 <span class="preprocessor"></span><span class="preprocessor">#define MAMXFLH (0x0B|0x40|0x80)</span> |
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| 119 | 00110 <span class="preprocessor"></span><span class="preprocessor">#define MAPHSUP (0x0D|0x40|0x80)</span> |
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| 120 | 00111 <span class="preprocessor"></span><span class="preprocessor">#define MICON (0x11|0x40|0x80)</span> |
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| 121 | 00112 <span class="preprocessor"></span><span class="preprocessor">#define MICMD (0x12|0x40|0x80)</span> |
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| 122 | 00113 <span class="preprocessor"></span><span class="preprocessor">#define MIREGADR (0x14|0x40|0x80)</span> |
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| 123 | 00114 <span class="preprocessor"></span><span class="preprocessor">#define MIWRL (0x16|0x40|0x80)</span> |
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| 124 | 00115 <span class="preprocessor"></span><span class="preprocessor">#define MIWRH (0x17|0x40|0x80)</span> |
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| 125 | 00116 <span class="preprocessor"></span><span class="preprocessor">#define MIRDL (0x18|0x40|0x80)</span> |
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| 126 | 00117 <span class="preprocessor"></span><span class="preprocessor">#define MIRDH (0x19|0x40|0x80)</span> |
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| 127 | 00118 <span class="preprocessor"></span><span class="comment">// Bank 3 registers</span> |
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| 128 | 00119 <span class="preprocessor">#define MAADR1 (0x00|0x60|0x80)</span> |
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| 129 | 00120 <span class="preprocessor"></span><span class="preprocessor">#define MAADR0 (0x01|0x60|0x80)</span> |
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| 130 | 00121 <span class="preprocessor"></span><span class="preprocessor">#define MAADR3 (0x02|0x60|0x80)</span> |
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| 131 | 00122 <span class="preprocessor"></span><span class="preprocessor">#define MAADR2 (0x03|0x60|0x80)</span> |
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| 132 | 00123 <span class="preprocessor"></span><span class="preprocessor">#define MAADR5 (0x04|0x60|0x80)</span> |
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| 133 | 00124 <span class="preprocessor"></span><span class="preprocessor">#define MAADR4 (0x05|0x60|0x80)</span> |
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| 134 | 00125 <span class="preprocessor"></span><span class="preprocessor">#define EBSTSD (0x06|0x60)</span> |
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| 135 | 00126 <span class="preprocessor"></span><span class="preprocessor">#define EBSTCON (0x07|0x60)</span> |
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| 136 | 00127 <span class="preprocessor"></span><span class="preprocessor">#define EBSTCSL (0x08|0x60)</span> |
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| 137 | 00128 <span class="preprocessor"></span><span class="preprocessor">#define EBSTCSH (0x09|0x60)</span> |
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| 138 | 00129 <span class="preprocessor"></span><span class="preprocessor">#define MISTAT (0x0A|0x60|0x80)</span> |
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| 139 | 00130 <span class="preprocessor"></span><span class="preprocessor">#define EREVID (0x12|0x60)</span> |
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| 140 | 00131 <span class="preprocessor"></span><span class="preprocessor">#define ECOCON (0x15|0x60)</span> |
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| 141 | 00132 <span class="preprocessor"></span><span class="preprocessor">#define EFLOCON (0x17|0x60)</span> |
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| 142 | 00133 <span class="preprocessor"></span><span class="preprocessor">#define EPAUSL (0x18|0x60)</span> |
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| 143 | 00134 <span class="preprocessor"></span><span class="preprocessor">#define EPAUSH (0x19|0x60)</span> |
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| 144 | 00135 <span class="preprocessor"></span><span class="comment">// PHY registers</span> |
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| 145 | 00136 <span class="preprocessor">#define PHCON1 0x00</span> |
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| 146 | 00137 <span class="preprocessor"></span><span class="preprocessor">#define PHSTAT1 0x01</span> |
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| 147 | 00138 <span class="preprocessor"></span><span class="preprocessor">#define PHHID1 0x02</span> |
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| 148 | 00139 <span class="preprocessor"></span><span class="preprocessor">#define PHHID2 0x03</span> |
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| 149 | 00140 <span class="preprocessor"></span><span class="preprocessor">#define PHCON2 0x10</span> |
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| 150 | 00141 <span class="preprocessor"></span><span class="preprocessor">#define PHSTAT2 0x11</span> |
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| 151 | 00142 <span class="preprocessor"></span><span class="preprocessor">#define PHIE 0x12</span> |
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| 152 | 00143 <span class="preprocessor"></span><span class="preprocessor">#define PHIR 0x13</span> |
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| 153 | 00144 <span class="preprocessor"></span><span class="preprocessor">#define PHLCON 0x14</span> |
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| 154 | 00145 <span class="preprocessor"></span> |
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| 155 | 00146 <span class="comment">// ENC28J60 EIE Register Bit Definitions</span> |
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| 156 | 00147 <span class="preprocessor">#define EIE_INTIE 0x80</span> |
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| 157 | 00148 <span class="preprocessor"></span><span class="preprocessor">#define EIE_PKTIE 0x40</span> |
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| 158 | 00149 <span class="preprocessor"></span><span class="preprocessor">#define EIE_DMAIE 0x20</span> |
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| 159 | 00150 <span class="preprocessor"></span><span class="preprocessor">#define EIE_LINKIE 0x10</span> |
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| 160 | 00151 <span class="preprocessor"></span><span class="preprocessor">#define EIE_TXIE 0x08</span> |
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| 161 | 00152 <span class="preprocessor"></span><span class="preprocessor">#define EIE_WOLIE 0x04</span> |
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| 162 | 00153 <span class="preprocessor"></span><span class="preprocessor">#define EIE_TXERIE 0x02</span> |
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| 163 | 00154 <span class="preprocessor"></span><span class="preprocessor">#define EIE_RXERIE 0x01</span> |
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| 164 | 00155 <span class="preprocessor"></span><span class="comment">// ENC28J60 EIR Register Bit Definitions</span> |
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| 165 | 00156 <span class="preprocessor">#define EIR_PKTIF 0x40</span> |
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| 166 | 00157 <span class="preprocessor"></span><span class="preprocessor">#define EIR_DMAIF 0x20</span> |
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| 167 | 00158 <span class="preprocessor"></span><span class="preprocessor">#define EIR_LINKIF 0x10</span> |
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| 168 | 00159 <span class="preprocessor"></span><span class="preprocessor">#define EIR_TXIF 0x08</span> |
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| 169 | 00160 <span class="preprocessor"></span><span class="preprocessor">#define EIR_WOLIF 0x04</span> |
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| 170 | 00161 <span class="preprocessor"></span><span class="preprocessor">#define EIR_TXERIF 0x02</span> |
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| 171 | 00162 <span class="preprocessor"></span><span class="preprocessor">#define EIR_RXERIF 0x01</span> |
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| 172 | 00163 <span class="preprocessor"></span><span class="comment">// ENC28J60 ESTAT Register Bit Definitions</span> |
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| 173 | 00164 <span class="preprocessor">#define ESTAT_INT 0x80</span> |
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| 174 | 00165 <span class="preprocessor"></span><span class="preprocessor">#define ESTAT_LATECOL 0x10</span> |
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| 175 | 00166 <span class="preprocessor"></span><span class="preprocessor">#define ESTAT_RXBUSY 0x04</span> |
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| 176 | 00167 <span class="preprocessor"></span><span class="preprocessor">#define ESTAT_TXABRT 0x02</span> |
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| 177 | 00168 <span class="preprocessor"></span><span class="preprocessor">#define ESTAT_CLKRDY 0x01</span> |
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| 178 | 00169 <span class="preprocessor"></span><span class="comment">// ENC28J60 ECON2 Register Bit Definitions</span> |
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| 179 | 00170 <span class="preprocessor">#define ECON2_AUTOINC 0x80</span> |
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| 180 | 00171 <span class="preprocessor"></span><span class="preprocessor">#define ECON2_PKTDEC 0x40</span> |
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| 181 | 00172 <span class="preprocessor"></span><span class="preprocessor">#define ECON2_PWRSV 0x20</span> |
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| 182 | 00173 <span class="preprocessor"></span><span class="preprocessor">#define ECON2_VRPS 0x08</span> |
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| 183 | 00174 <span class="preprocessor"></span><span class="comment">// ENC28J60 ECON1 Register Bit Definitions</span> |
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| 184 | 00175 <span class="preprocessor">#define ECON1_TXRST 0x80</span> |
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| 185 | 00176 <span class="preprocessor"></span><span class="preprocessor">#define ECON1_RXRST 0x40</span> |
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| 186 | 00177 <span class="preprocessor"></span><span class="preprocessor">#define ECON1_DMAST 0x20</span> |
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| 187 | 00178 <span class="preprocessor"></span><span class="preprocessor">#define ECON1_CSUMEN 0x10</span> |
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| 188 | 00179 <span class="preprocessor"></span><span class="preprocessor">#define ECON1_TXRTS 0x08</span> |
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| 189 | 00180 <span class="preprocessor"></span><span class="preprocessor">#define ECON1_RXEN 0x04</span> |
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| 190 | 00181 <span class="preprocessor"></span><span class="preprocessor">#define ECON1_BSEL1 0x02</span> |
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| 191 | 00182 <span class="preprocessor"></span><span class="preprocessor">#define ECON1_BSEL0 0x01</span> |
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| 192 | 00183 <span class="preprocessor"></span><span class="comment">// ENC28J60 MACON1 Register Bit Definitions</span> |
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| 193 | 00184 <span class="preprocessor">#define MACON1_LOOPBK 0x10</span> |
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| 194 | 00185 <span class="preprocessor"></span><span class="preprocessor">#define MACON1_TXPAUS 0x08</span> |
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| 195 | 00186 <span class="preprocessor"></span><span class="preprocessor">#define MACON1_RXPAUS 0x04</span> |
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| 196 | 00187 <span class="preprocessor"></span><span class="preprocessor">#define MACON1_PASSALL 0x02</span> |
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| 197 | 00188 <span class="preprocessor"></span><span class="preprocessor">#define MACON1_MARXEN 0x01</span> |
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| 198 | 00189 <span class="preprocessor"></span><span class="comment">// ENC28J60 MACON2 Register Bit Definitions</span> |
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| 199 | 00190 <span class="preprocessor">#define MACON2_MARST 0x80</span> |
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| 200 | 00191 <span class="preprocessor"></span><span class="preprocessor">#define MACON2_RNDRST 0x40</span> |
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| 201 | 00192 <span class="preprocessor"></span><span class="preprocessor">#define MACON2_MARXRST 0x08</span> |
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| 202 | 00193 <span class="preprocessor"></span><span class="preprocessor">#define MACON2_RFUNRST 0x04</span> |
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| 203 | 00194 <span class="preprocessor"></span><span class="preprocessor">#define MACON2_MATXRST 0x02</span> |
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| 204 | 00195 <span class="preprocessor"></span><span class="preprocessor">#define MACON2_TFUNRST 0x01</span> |
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| 205 | 00196 <span class="preprocessor"></span><span class="comment">// ENC28J60 MACON3 Register Bit Definitions</span> |
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| 206 | 00197 <span class="preprocessor">#define MACON3_PADCFG2 0x80</span> |
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| 207 | 00198 <span class="preprocessor"></span><span class="preprocessor">#define MACON3_PADCFG1 0x40</span> |
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| 208 | 00199 <span class="preprocessor"></span><span class="preprocessor">#define MACON3_PADCFG0 0x20</span> |
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| 209 | 00200 <span class="preprocessor"></span><span class="preprocessor">#define MACON3_TXCRCEN 0x10</span> |
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| 210 | 00201 <span class="preprocessor"></span><span class="preprocessor">#define MACON3_PHDRLEN 0x08</span> |
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| 211 | 00202 <span class="preprocessor"></span><span class="preprocessor">#define MACON3_HFRMLEN 0x04</span> |
||
| 212 | 00203 <span class="preprocessor"></span><span class="preprocessor">#define MACON3_FRMLNEN 0x02</span> |
||
| 213 | 00204 <span class="preprocessor"></span><span class="preprocessor">#define MACON3_FULDPX 0x01</span> |
||
| 214 | 00205 <span class="preprocessor"></span><span class="comment">// ENC28J60 MICMD Register Bit Definitions</span> |
||
| 215 | 00206 <span class="preprocessor">#define MICMD_MIISCAN 0x02</span> |
||
| 216 | 00207 <span class="preprocessor"></span><span class="preprocessor">#define MICMD_MIIRD 0x01</span> |
||
| 217 | 00208 <span class="preprocessor"></span><span class="comment">// ENC28J60 MISTAT Register Bit Definitions</span> |
||
| 218 | 00209 <span class="preprocessor">#define MISTAT_NVALID 0x04</span> |
||
| 219 | 00210 <span class="preprocessor"></span><span class="preprocessor">#define MISTAT_SCAN 0x02</span> |
||
| 220 | 00211 <span class="preprocessor"></span><span class="preprocessor">#define MISTAT_BUSY 0x01</span> |
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| 221 | 00212 <span class="preprocessor"></span><span class="comment">// ENC28J60 PHY PHCON1 Register Bit Definitions</span> |
||
| 222 | 00213 <span class="preprocessor">#define PHCON1_PRST 0x8000</span> |
||
| 223 | 00214 <span class="preprocessor"></span><span class="preprocessor">#define PHCON1_PLOOPBK 0x4000</span> |
||
| 224 | 00215 <span class="preprocessor"></span><span class="preprocessor">#define PHCON1_PPWRSV 0x0800</span> |
||
| 225 | 00216 <span class="preprocessor"></span><span class="preprocessor">#define PHCON1_PDPXMD 0x0100</span> |
||
| 226 | 00217 <span class="preprocessor"></span><span class="comment">// ENC28J60 PHY PHSTAT1 Register Bit Definitions</span> |
||
| 227 | 00218 <span class="preprocessor">#define PHSTAT1_PFDPX 0x1000</span> |
||
| 228 | 00219 <span class="preprocessor"></span><span class="preprocessor">#define PHSTAT1_PHDPX 0x0800</span> |
||
| 229 | 00220 <span class="preprocessor"></span><span class="preprocessor">#define PHSTAT1_LLSTAT 0x0004</span> |
||
| 230 | 00221 <span class="preprocessor"></span><span class="preprocessor">#define PHSTAT1_JBSTAT 0x0002</span> |
||
| 231 | 00222 <span class="preprocessor"></span><span class="comment">// ENC28J60 PHY PHCON2 Register Bit Definitions</span> |
||
| 232 | 00223 <span class="preprocessor">#define PHCON2_FRCLINK 0x4000</span> |
||
| 233 | 00224 <span class="preprocessor"></span><span class="preprocessor">#define PHCON2_TXDIS 0x2000</span> |
||
| 234 | 00225 <span class="preprocessor"></span><span class="preprocessor">#define PHCON2_JABBER 0x0400</span> |
||
| 235 | 00226 <span class="preprocessor"></span><span class="preprocessor">#define PHCON2_HDLDIS 0x0100</span> |
||
| 236 | 00227 <span class="preprocessor"></span> |
||
| 237 | 00228 <span class="comment">// ENC28J60 Packet Control Byte Bit Definitions</span> |
||
| 238 | 00229 <span class="preprocessor">#define PKTCTRL_PHUGEEN 0x08</span> |
||
| 239 | 00230 <span class="preprocessor"></span><span class="preprocessor">#define PKTCTRL_PPADEN 0x04</span> |
||
| 240 | 00231 <span class="preprocessor"></span><span class="preprocessor">#define PKTCTRL_PCRCEN 0x02</span> |
||
| 241 | 00232 <span class="preprocessor"></span><span class="preprocessor">#define PKTCTRL_POVERRIDE 0x01</span> |
||
| 242 | 00233 <span class="preprocessor"></span> |
||
| 243 | 00234 <span class="comment">// SPI operation codes</span> |
||
| 244 | 00235 <span class="preprocessor">#define ENC28J60_READ_CTRL_REG 0x00</span> |
||
| 245 | 00236 <span class="preprocessor"></span><span class="preprocessor">#define ENC28J60_READ_BUF_MEM 0x3A</span> |
||
| 246 | 00237 <span class="preprocessor"></span><span class="preprocessor">#define ENC28J60_WRITE_CTRL_REG 0x40</span> |
||
| 247 | 00238 <span class="preprocessor"></span><span class="preprocessor">#define ENC28J60_WRITE_BUF_MEM 0x7A</span> |
||
| 248 | 00239 <span class="preprocessor"></span><span class="preprocessor">#define ENC28J60_BIT_FIELD_SET 0x80</span> |
||
| 249 | 00240 <span class="preprocessor"></span><span class="preprocessor">#define ENC28J60_BIT_FIELD_CLR 0xA0</span> |
||
| 250 | 00241 <span class="preprocessor"></span><span class="preprocessor">#define ENC28J60_SOFT_RESET 0xFF</span> |
||
| 251 | 00242 <span class="preprocessor"></span> |
||
| 252 | 00243 |
||
| 253 | 00244 <span class="comment">// buffer boundaries applied to internal 8K ram</span> |
||
| 254 | 00245 <span class="comment">// entire available packet buffer space is allocated</span> |
||
| 255 | 00246 <span class="preprocessor">#define TXSTART_INIT 0x0000 // start TX buffer at 0</span> |
||
| 256 | 00247 <span class="preprocessor"></span><span class="preprocessor">#define RXSTART_INIT 0x0600 // give TX buffer space for one full ethernet frame (~1500 bytes)</span> |
||
| 257 | 00248 <span class="preprocessor"></span><span class="preprocessor">#define RXSTOP_INIT 0x1FFF // receive buffer gets the rest</span> |
||
| 258 | 00249 <span class="preprocessor"></span> |
||
| 259 | 00250 <span class="preprocessor">#define MAX_FRAMELEN 1518 // maximum ethernet frame length</span> |
||
| 260 | 00251 <span class="preprocessor"></span> |
||
| 261 | 00252 <span class="comment">// Ethernet constants</span> |
||
| 262 | 00253 <span class="preprocessor">#define ETHERNET_MIN_PACKET_LENGTH 0x3C</span> |
||
| 263 | 00254 <span class="preprocessor"></span><span class="comment">//#define ETHERNET_HEADER_LENGTH 0x0E</span> |
||
| 264 | 00255 |
||
| 265 | 00256 <span class="comment">// functions</span> |
||
| 266 | 00257 <span class="preprocessor">#include "<a class="code" href="nic_8h.html">nic.h</a>"</span> |
||
| 267 | 00258 |
||
| 268 | 00259 <span class="comment">// setup ports for I/O</span> |
||
| 269 | 00260 <span class="comment">//void ax88796SetupPorts(void);</span> |
||
| 270 | 00261 <span class="comment"></span> |
||
| 271 | 00262 <span class="comment">//! do a ENC28J60 read operation</span> |
||
| 272 | 00263 <span class="comment"></span>u08 <a class="code" href="group__enc28j60.html#ga0">enc28j60ReadOp</a>(u08 <a class="code" href="structnetBootpHeader.html#o0">op</a>, u08 address);<span class="comment"></span> |
||
| 273 | 00264 <span class="comment">//! do a ENC28J60 write operation</span> |
||
| 274 | 00265 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(u08 <a class="code" href="structnetBootpHeader.html#o0">op</a>, u08 address, u08 data);<span class="comment"></span> |
||
| 275 | 00266 <span class="comment">//! read the packet buffer memory</span> |
||
| 276 | 00267 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga2">enc28j60ReadBuffer</a>(u16 len, u08* data);<span class="comment"></span> |
||
| 277 | 00268 <span class="comment">//! write the packet buffer memory</span> |
||
| 278 | 00269 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga3">enc28j60WriteBuffer</a>(u16 len, u08* data);<span class="comment"></span> |
||
| 279 | 00270 <span class="comment">//! set the register bank for register at address</span> |
||
| 280 | 00271 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga4">enc28j60SetBank</a>(u08 address);<span class="comment"></span> |
||
| 281 | 00272 <span class="comment">//! read ax88796 register</span> |
||
| 282 | 00273 <span class="comment"></span>u08 <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(u08 address);<span class="comment"></span> |
||
| 283 | 00274 <span class="comment">//! write ax88796 register</span> |
||
| 284 | 00275 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(u08 address, u08 data);<span class="comment"></span> |
||
| 285 | 00276 <span class="comment">//! read a PHY register</span> |
||
| 286 | 00277 <span class="comment"></span>u16 <a class="code" href="group__enc28j60.html#ga7">enc28j60PhyRead</a>(u08 address);<span class="comment"></span> |
||
| 287 | 00278 <span class="comment">//! write a PHY register</span> |
||
| 288 | 00279 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga8">enc28j60PhyWrite</a>(u08 address, u16 data); |
||
| 289 | 00280 <span class="comment"></span> |
||
| 290 | 00281 <span class="comment">//! initialize the ethernet interface for transmit/receive</span> |
||
| 291 | 00282 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga9">enc28j60Init</a>(<span class="keywordtype">void</span>); |
||
| 292 | 00283 <span class="comment"></span> |
||
| 293 | 00284 <span class="comment">//! Packet transmit function.</span> |
||
| 294 | 00285 <span class="comment">/// Sends a packet on the network. It is assumed that the packet is headed by a valid ethernet header.</span> |
||
| 295 | 00286 <span class="comment">/// \param len Length of packet in bytes.</span> |
||
| 296 | 00287 <span class="comment">/// \param packet Pointer to packet data.</span> |
||
| 297 | 00288 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga10">enc28j60PacketSend</a>(<span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> len, <span class="keywordtype">unsigned</span> <span class="keywordtype">char</span>* packet); |
||
| 298 | 00289 <span class="comment"></span> |
||
| 299 | 00290 <span class="comment">//! Packet receive function.</span> |
||
| 300 | 00291 <span class="comment">/// Gets a packet from the network receive buffer, if one is available.</span> |
||
| 301 | 00292 <span class="comment">/// The packet will by headed by an ethernet header.</span> |
||
| 302 | 00293 <span class="comment">/// \param maxlen The maximum acceptable length of a retrieved packet.</span> |
||
| 303 | 00294 <span class="comment">/// \param packet Pointer where packet data should be stored.</span> |
||
| 304 | 00295 <span class="comment">/// \return Packet length in bytes if a packet was retrieved, zero otherwise.</span> |
||
| 305 | 00296 <span class="comment"></span><span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> <a class="code" href="group__enc28j60.html#ga11">enc28j60PacketReceive</a>(<span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> maxlen, <span class="keywordtype">unsigned</span> <span class="keywordtype">char</span>* packet); |
||
| 306 | 00297 <span class="comment"></span> |
||
| 307 | 00298 <span class="comment">//! execute procedure for recovering from a receive overflow</span> |
||
| 308 | 00299 <span class="comment">/// this should be done when the receive memory fills up with packets</span> |
||
| 309 | 00300 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga12">enc28j60ReceiveOverflowRecover</a>(<span class="keywordtype">void</span>); |
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| 310 | 00301 <span class="comment"></span> |
||
| 311 | 00302 <span class="comment">//! formatted print of important ENC28J60 registers</span> |
||
| 312 | 00303 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga13">enc28j60RegDump</a>(<span class="keywordtype">void</span>); |
||
| 313 | 00304 |
||
| 314 | 00305 <span class="preprocessor">#endif</span> |
||
| 315 | 00306 <span class="preprocessor"></span><span class="comment">//@}</span> |
||
| 316 | </span></pre></div><hr size="1"><address style="align: right;"><small>Generated on Sun Oct 29 03:41:07 2006 for Procyon AVRlib by |
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| 317 | <a href="http://www.doxygen.org/index.html"> |
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| 318 | <img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.2 </small></address> |
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| 319 | </body> |
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| 320 | </html> |
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