?lang_form? ?lang_select? ?lang_submit? ?lang_endform?
{HEADER END}
{BLAME START}

library

?curdirlinks? -

Blame information for rev 6

Line No. Rev Author Line
1 6 kaklik <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
2 <html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
3 <title>Procyon AVRlib: net/ax88796.h Source File</title>
4 <link href="dox.css" rel="stylesheet" type="text/css">
5 </head><body>
6 <!-- Generated by Doxygen 1.4.2 -->
7 <div class="qindex"><a class="qindex" href="main.html">Main&nbsp;Page</a> | <a class="qindex" href="modules.html">Modules</a> | <a class="qindex" href="annotated.html">Data&nbsp;Structures</a> | <a class="qindex" href="dirs.html">Directories</a> | <a class="qindex" href="files.html">File&nbsp;List</a> | <a class="qindex" href="functions.html">Data&nbsp;Fields</a> | <a class="qindex" href="globals.html">Globals</a> | <a class="qindex" href="pages.html">Related&nbsp;Pages</a></div>
8 <div class="nav">
9 <a class="el" href="dir_000001.html">net</a></div>
10 <h1>ax88796.h</h1><a href="ax88796_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment">00001 <span class="comment">/*! \file ax88796.h \brief ASIX AX88796 Ethernet Interface Driver. */</span>
11 00002 <span class="comment">//*****************************************************************************</span>
12 00003 <span class="comment">//</span>
13 00004 <span class="comment">// File Name : 'ax88796.h'</span>
14 00005 <span class="comment">// Title : ASIX AX88796 Ethernet Interface Driver</span>
15 00006 <span class="comment">// Author : Pascal Stang</span>
16 00007 <span class="comment">// Created : 10/22/2002</span>
17 00008 <span class="comment">// Revised : 8/22/2005</span>
18 00009 <span class="comment">// Version : 0.1</span>
19 00010 <span class="comment">// Target MCU : Atmel AVR series</span>
20 00011 <span class="comment">// Editor Tabs : 4</span>
21 00012 <span class="comment">//</span><span class="comment"></span>
22 00013 <span class="comment">/// \ingroup network</span>
23 00014 <span class="comment">/// \defgroup ax88796 ASIX AX88796 Ethernet Interface Driver (ax88796.c)</span>
24 00015 <span class="comment">/// \code #include "net/ax88796.h" \endcode</span>
25 00016 <span class="comment">/// \par Overview</span>
26 00017 <span class="comment">/// This driver provides initialization and transmit/receive</span>
27 00018 <span class="comment">/// functions for the ASIX AX88796 10/100Mb Ethernet Controller and PHY.</span>
28 00019 <span class="comment">///</span>
29 00020 <span class="comment">/// Based in part on code by Louis Beaudoin (www.embedded-creations.com).</span>
30 00021 <span class="comment">/// Thanks to Adam Dunkels and Louis Beaudoin for providing the initial</span>
31 00022 <span class="comment">/// structure in which to write this driver.</span>
32 00023 <span class="comment"></span><span class="comment">//</span>
33 00024 <span class="comment">//*****************************************************************************</span><span class="comment"></span>
34 00025 <span class="comment">//@{</span>
35 00026 <span class="comment"></span>
36 00027 <span class="preprocessor">#ifndef AX88796_H</span>
37 00028 <span class="preprocessor"></span><span class="preprocessor">#define AX88796_H</span>
38 00029 <span class="preprocessor"></span>
39 00030 <span class="preprocessor">#include "<a class="code" href="global_8h.html">global.h</a>"</span>
40 00031
41 00032 <span class="preprocessor">#define nop() asm volatile ("nop")</span>
42 00033 <span class="preprocessor"></span>
43 00034 <span class="comment">// AX88796/NE2000 Control Register Offsets</span>
44 00035 <span class="comment">// Page 0 - Read/Write</span>
45 00036 <span class="preprocessor">#define CR 0x00 // Command Register</span>
46 00037 <span class="preprocessor"></span><span class="preprocessor">#define PSTART 0x01 // Page Start Register</span>
47 00038 <span class="preprocessor"></span><span class="preprocessor">#define PSTOP 0x02 // Page Stop Register</span>
48 00039 <span class="preprocessor"></span><span class="preprocessor">#define BNRY 0x03 // Boundary Pointer</span>
49 00040 <span class="preprocessor"></span><span class="preprocessor">#define RDMAPORT 0x10 // DMA Data Port</span>
50 00041 <span class="preprocessor"></span><span class="preprocessor">#define MEMR 0x14 // MII/EEPROM Access Register</span>
51 00042 <span class="preprocessor"></span><span class="preprocessor">#define TR 0x15 // Test Register</span>
52 00043 <span class="preprocessor"></span><span class="preprocessor">#define SPP_DPR 0x18 // Standard Printer Port Data</span>
53 00044 <span class="preprocessor"></span><span class="preprocessor">#define SSP_SPR 0x19 // Standard Printer Port Status</span>
54 00045 <span class="preprocessor"></span><span class="preprocessor">#define SSP_CPR 0x1A // Standard Printer Port Control</span>
55 00046 <span class="preprocessor"></span><span class="comment">// Page 0 - Read</span>
56 00047 <span class="preprocessor">#define TSR 0x04 // Transmit Status Register</span>
57 00048 <span class="preprocessor"></span><span class="preprocessor">#define NCR 0x05 // Number of Collisions Register</span>
58 00049 <span class="preprocessor"></span><span class="preprocessor">#define ISR 0x07 // Interrupt Status Register</span>
59 00050 <span class="preprocessor"></span><span class="preprocessor">#define CRDA0 0x08 // Current Remote DMA Address 0</span>
60 00051 <span class="preprocessor"></span><span class="preprocessor">#define CRDA1 0x09 // Current Remote DMA Address 1</span>
61 00052 <span class="preprocessor"></span><span class="preprocessor">#define RSR 0x0C // Receive Status Register</span>
62 00053 <span class="preprocessor"></span><span class="preprocessor">#define CNTR0 0x0D</span>
63 00054 <span class="preprocessor"></span><span class="preprocessor">#define CNTR1 0x0E</span>
64 00055 <span class="preprocessor"></span><span class="preprocessor">#define CNTR2 0x0F</span>
65 00056 <span class="preprocessor"></span><span class="preprocessor">#define GPI 0x17 // General-Purpose Input</span>
66 00057 <span class="preprocessor"></span><span class="preprocessor">#define RSTPORT 0x1F // Reset</span>
67 00058 <span class="preprocessor"></span><span class="comment">// Page 0 - Write</span>
68 00059 <span class="preprocessor">#define TPSR 0x04 // Transmit Page Start Address</span>
69 00060 <span class="preprocessor"></span><span class="preprocessor">#define TBCR0 0x05 // Transmit Byte Count Register 0</span>
70 00061 <span class="preprocessor"></span><span class="preprocessor">#define TBCR1 0x06 // Transmit Byte Count Register 1</span>
71 00062 <span class="preprocessor"></span><span class="preprocessor">#define RSAR0 0x08 // Remote Start Address Register 0</span>
72 00063 <span class="preprocessor"></span><span class="preprocessor">#define RSAR1 0x09 // Remote Start Address Register 1</span>
73 00064 <span class="preprocessor"></span><span class="preprocessor">#define RBCR0 0x0A // Remote Byte Count 0</span>
74 00065 <span class="preprocessor"></span><span class="preprocessor">#define RBCR1 0x0B // Remote Byte Count 1</span>
75 00066 <span class="preprocessor"></span><span class="preprocessor">#define RCR 0x0C // Receive Config Register</span>
76 00067 <span class="preprocessor"></span><span class="preprocessor">#define TCR 0x0D // Transmit Config Register</span>
77 00068 <span class="preprocessor"></span><span class="preprocessor">#define DCR 0x0E // Data Config Register</span>
78 00069 <span class="preprocessor"></span><span class="preprocessor">#define IMR 0x0F // Interrupt Mask Register</span>
79 00070 <span class="preprocessor"></span><span class="preprocessor">#define GPOC 0x17 // General-Purpose Output Control</span>
80 00071 <span class="preprocessor"></span><span class="comment">// Page 1 - Read/Write</span>
81 00072 <span class="preprocessor">#define PAR0 0x01 // Physical Address Register 0</span>
82 00073 <span class="preprocessor"></span><span class="preprocessor">#define PAR1 0x02 // Physical Address Register 0</span>
83 00074 <span class="preprocessor"></span><span class="preprocessor">#define PAR2 0x03 // Physical Address Register 0</span>
84 00075 <span class="preprocessor"></span><span class="preprocessor">#define PAR3 0x04 // Physical Address Register 0</span>
85 00076 <span class="preprocessor"></span><span class="preprocessor">#define PAR4 0x05 // Physical Address Register 0</span>
86 00077 <span class="preprocessor"></span><span class="preprocessor">#define PAR5 0x06 // Physical Address Register 0</span>
87 00078 <span class="preprocessor"></span><span class="preprocessor">#define CURR 0x07 // Page 1</span>
88 00079 <span class="preprocessor"></span><span class="preprocessor">#define CPR 0x07 // Current Page Register</span>
89 00080 <span class="preprocessor"></span>
90 00081 <span class="comment">// AX88796 CR Register Bit Definitions</span>
91 00082 <span class="preprocessor">#define PS1 0x80 </span>
92 00083 <span class="preprocessor"></span><span class="preprocessor">#define PS0 0x40 </span>
93 00084 <span class="preprocessor"></span><span class="preprocessor">#define RD2 0x20 </span>
94 00085 <span class="preprocessor"></span><span class="preprocessor">#define RD1 0x10 </span>
95 00086 <span class="preprocessor"></span><span class="preprocessor">#define RD0 0x08 </span>
96 00087 <span class="preprocessor"></span><span class="preprocessor">#define TXP 0x04 </span>
97 00088 <span class="preprocessor"></span><span class="preprocessor">#define START 0x02 </span>
98 00089 <span class="preprocessor"></span><span class="preprocessor">#define STOP 0x01 </span>
99 00090 <span class="preprocessor"></span><span class="comment">// AX88796 RCR Register Bit Definitions</span>
100 00091 <span class="preprocessor">#define INTT 0x40 </span>
101 00092 <span class="preprocessor"></span><span class="preprocessor">#define MON 0x20 </span>
102 00093 <span class="preprocessor"></span><span class="preprocessor">#define PRO 0x10 </span>
103 00094 <span class="preprocessor"></span><span class="preprocessor">#define AM 0x08 </span>
104 00095 <span class="preprocessor"></span><span class="preprocessor">#define AB 0x04 </span>
105 00096 <span class="preprocessor"></span><span class="preprocessor">#define AR 0x02 </span>
106 00097 <span class="preprocessor"></span><span class="preprocessor">#define SEP 0x01 </span>
107 00098 <span class="preprocessor"></span><span class="comment">// AX88796 ISR Register Bit Definitions</span>
108 00099 <span class="preprocessor">#define RST 0x80</span>
109 00100 <span class="preprocessor"></span><span class="preprocessor">#define RDC 0x40</span>
110 00101 <span class="preprocessor"></span><span class="preprocessor">#define OVW 0x10</span>
111 00102 <span class="preprocessor"></span><span class="preprocessor">#define RXE 0x08</span>
112 00103 <span class="preprocessor"></span><span class="preprocessor">#define TXE 0x04</span>
113 00104 <span class="preprocessor"></span><span class="preprocessor">#define PTX 0x02</span>
114 00105 <span class="preprocessor"></span><span class="preprocessor">#define PRX 0x01</span>
115 00106 <span class="preprocessor"></span><span class="comment">// AX88796 TEST Register Bit Definitions</span>
116 00107 <span class="preprocessor">#define AUTOD 0x01 </span>
117 00108 <span class="preprocessor"></span><span class="preprocessor">#define RST_B 0x02</span>
118 00109 <span class="preprocessor"></span><span class="preprocessor">#define RST_10B 0x04</span>
119 00110 <span class="preprocessor"></span><span class="preprocessor">#define RST_TXB 0x08</span>
120 00111 <span class="preprocessor"></span><span class="comment">// AX88796 GPOC Register Bit Definitions</span>
121 00112 <span class="preprocessor">#define GPO0 0x01</span>
122 00113 <span class="preprocessor"></span><span class="preprocessor">#define MPSEL 0x10</span>
123 00114 <span class="preprocessor"></span><span class="preprocessor">#define MPSET 0x20</span>
124 00115 <span class="preprocessor"></span><span class="preprocessor">#define PPDSET 0x40</span>
125 00116 <span class="preprocessor"></span><span class="comment">// AX88796 MEMR Register Bit Definitions</span>
126 00117 <span class="preprocessor">#define MDC 0x01</span>
127 00118 <span class="preprocessor"></span><span class="preprocessor">#define MDIR 0x02</span>
128 00119 <span class="preprocessor"></span><span class="preprocessor">#define MDI 0x04</span>
129 00120 <span class="preprocessor"></span><span class="preprocessor">#define MDO 0x08</span>
130 00121 <span class="preprocessor"></span><span class="preprocessor">#define EECS 0x10</span>
131 00122 <span class="preprocessor"></span><span class="preprocessor">#define EEI 0x20</span>
132 00123 <span class="preprocessor"></span><span class="preprocessor">#define EEO 0x40</span>
133 00124 <span class="preprocessor"></span><span class="preprocessor">#define EECLK 0x80</span>
134 00125 <span class="preprocessor"></span><span class="comment">// AX88796 GPI Register Bit Definitions</span>
135 00126 <span class="preprocessor">#define GPI2 0x40</span>
136 00127 <span class="preprocessor"></span><span class="preprocessor">#define GPI1 0x20</span>
137 00128 <span class="preprocessor"></span><span class="preprocessor">#define GPI0 0x10</span>
138 00129 <span class="preprocessor"></span><span class="preprocessor">#define I_SPD 0x04</span>
139 00130 <span class="preprocessor"></span><span class="preprocessor">#define I_DPX 0x02</span>
140 00131 <span class="preprocessor"></span><span class="preprocessor">#define I_LINK 0x01</span>
141 00132 <span class="preprocessor"></span><span class="comment">// AX88796 TCR Register Bit Definitions</span>
142 00133 <span class="preprocessor">#define FDU 0x80 // full duplex</span>
143 00134 <span class="preprocessor"></span><span class="preprocessor">#define PD 0x40 // pad disable</span>
144 00135 <span class="preprocessor"></span><span class="preprocessor">#define RLO 0x20 // retry of late collisions</span>
145 00136 <span class="preprocessor"></span><span class="preprocessor">#define LB1 0x04 // loopback 1</span>
146 00137 <span class="preprocessor"></span><span class="preprocessor">#define LB0 0x02 // loopback 0</span>
147 00138 <span class="preprocessor"></span><span class="preprocessor">#define CRC 0x01 // generate CRC</span>
148 00139 <span class="preprocessor"></span>
149 00140 <span class="comment">// AX88796 Initial Register Values</span>
150 00141 <span class="comment">// RCR : INT trigger active high and Accept Broadcast ENET packets</span>
151 00142 <span class="preprocessor">#define RCR_INIT (INTT | AB)</span>
152 00143 <span class="preprocessor"></span><span class="preprocessor">#define DCR_INIT 0x00 // was 0x58 for realtek RTL8019</span>
153 00144 <span class="preprocessor"></span><span class="comment">// TCR : default transmit operation - CRC is generated</span>
154 00145 <span class="preprocessor">#define TCR_INIT 0x00</span>
155 00146 <span class="preprocessor"></span><span class="comment">// IMR : interrupt enabled for receive and overrun events</span>
156 00147 <span class="preprocessor">#define IMR_INIT 0x11 // PRX and OVW interrupt enabled</span>
157 00148 <span class="preprocessor"></span><span class="comment">// buffer boundaries</span>
158 00149 <span class="comment">// transmit has 6 256-byte pages</span>
159 00150 <span class="comment">// receive has 26 256-byte pages</span>
160 00151 <span class="comment">// entire available packet buffer space is allocated</span>
161 00152 <span class="preprocessor">#define TXSTART_INIT 0x40</span>
162 00153 <span class="preprocessor"></span><span class="preprocessor">#define RXSTART_INIT 0x46</span>
163 00154 <span class="preprocessor"></span><span class="preprocessor">#define RXSTOP_INIT 0x60</span>
164 00155 <span class="preprocessor"></span>
165 00156 <span class="comment">// Ethernet constants</span>
166 00157 <span class="preprocessor">#define ETHERNET_MIN_PACKET_LENGTH 0x3C</span>
167 00158 <span class="preprocessor"></span><span class="comment">//#define ETHERNET_HEADER_LENGTH 0x0E</span>
168 00159
169 00160 <span class="comment">// offsets into ax88796 ethernet packet header</span>
170 00161 <span class="preprocessor">#define PKTHEADER_STATUS 0x00 // packet status</span>
171 00162 <span class="preprocessor"></span><span class="preprocessor">#define PKTHEADER_NEXTPAGE 0x01 // next buffer page</span>
172 00163 <span class="preprocessor"></span><span class="preprocessor">#define PKTHEADER_PKTLENL 0x02 // packet length low</span>
173 00164 <span class="preprocessor"></span><span class="preprocessor">#define PKTHEADER_PKTLENH 0x03 // packet length high</span>
174 00165 <span class="preprocessor"></span>
175 00166
176 00167 <span class="comment">// functions</span>
177 00168 <span class="preprocessor">#include "<a class="code" href="nic_8h.html">nic.h</a>"</span>
178 00169
179 00170 <span class="comment">// setup ports for I/O</span>
180 00171 <span class="keywordtype">void</span> ax88796SetupPorts(<span class="keywordtype">void</span>);
181 00172
182 00173 <span class="comment">// read ax88796 register</span>
183 00174 u08 ax88796Read(u08 address);
184 00175
185 00176 <span class="comment">// write ax88796 register</span>
186 00177 <span class="keywordtype">void</span> ax88796Write(u08 address, u08 data);
187 00178
188 00179 <span class="comment">// initialize the ethernet interface for transmit/receive</span>
189 00180 <span class="keywordtype">void</span> ax88796Init(<span class="keywordtype">void</span>);
190 00181
191 00182 <span class="comment">// packet transmit functions</span>
192 00183 <span class="keywordtype">void</span> ax88796BeginPacketSend(<span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> packetLength);
193 00184 <span class="keywordtype">void</span> ax88796SendPacketData(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> * localBuffer, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> length);
194 00185 <span class="keywordtype">void</span> ax88796EndPacketSend(<span class="keywordtype">void</span>);
195 00186
196 00187 <span class="comment">// packet receive functions</span>
197 00188 <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> ax88796BeginPacketRetreive(<span class="keywordtype">void</span>);
198 00189 <span class="keywordtype">void</span> ax88796RetreivePacketData(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> *localBuffer, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> length);
199 00190 <span class="keywordtype">void</span> ax88796EndPacketRetreive(<span class="keywordtype">void</span>);
200 00191
201 00192 <span class="comment">// Processes AX88796 interrupts.</span>
202 00193 <span class="comment">// Currently, this function looks only for a receive overflow condition.</span>
203 00194 <span class="comment">// The function need not be called in response to an interrupt,</span>
204 00195 <span class="comment">// but can be executed just before checking the receive buffer for incoming packets.</span>
205 00196 <span class="keywordtype">void</span> ax88796ProcessInterrupt(<span class="keywordtype">void</span>);
206 00197
207 00198 <span class="comment">// execute procedure for recovering from a receive overflow</span>
208 00199 <span class="comment">// this should be done when the receive memory fills up with packets</span>
209 00200 <span class="keywordtype">void</span> ax88796ReceiveOverflowRecover(<span class="keywordtype">void</span>);
210 00201
211 00202 <span class="comment">// Write MII Registers</span>
212 00203 <span class="keywordtype">void</span> ax88796WriteMii(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> phyad,<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> regad,<span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> mii_data);
213 00204 <span class="comment">// Read MII Registers</span>
214 00205 <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> ax88796ReadMii(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> phyad,<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> regad);
215 00206
216 00207 <span class="comment">// formatted print of all important AX88796 registers</span>
217 00208 <span class="keywordtype">void</span> ax88796RegDump(<span class="keywordtype">void</span>);
218 00209
219 00210 <span class="preprocessor">#endif</span>
220 00211 <span class="preprocessor"></span><span class="comment">//@}</span>
221 </span></pre></div><hr size="1"><address style="align: right;"><small>Generated on Sun Oct 29 03:41:07 2006 for Procyon AVRlib by&nbsp;
222 <a href="http://www.doxygen.org/index.html">
223 <img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.2 </small></address>
224 </body>
225 </html>
{BLAME END}
{FOOTER START}

Powered by WebSVN v2.8.3