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Blame information for rev 32

Line No. Rev Author Line
1 32 kaklik /*********************************************************************
2 *
3 * Ethernet registers/bits for PIC18F97J60
4 *
5 *********************************************************************
6 * FileName: ETH97J60.h
7 * Dependencies: None
8 * Processor: PIC18F97J60 Family
9 * Compiler: Microchip C18 v3.30 or higher
10 * HI-TECH PICC-18 PRO 9.63PL2 or higher
11 * Company: Microchip Technology, Inc.
12 *
13 * Software License Agreement
14 *
15 * Copyright (C) 2002-2009 Microchip Technology Inc. All rights
16 * reserved.
17 *
18 * Microchip licenses to you the right to use, modify, copy, and
19 * distribute:
20 * (i) the Software when embedded on a Microchip microcontroller or
21 * digital signal controller product ("Device") which is
22 * integrated into Licensee's product; or
23 * (ii) ONLY the Software driver source files ENC28J60.c, ENC28J60.h,
24 * ENCX24J600.c and ENCX24J600.h ported to a non-Microchip device
25 * used in conjunction with a Microchip ethernet controller for
26 * the sole purpose of interfacing with the ethernet controller.
27 *
28 * You should refer to the license agreement accompanying this
29 * Software for additional information regarding your rights and
30 * obligations.
31 *
32 * THE SOFTWARE AND DOCUMENTATION ARE PROVIDED "AS IS" WITHOUT
33 * WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT
34 * LIMITATION, ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A
35 * PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL
36 * MICROCHIP BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR
37 * CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF
38 * PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
39 * BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE
40 * THEREOF), ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER
41 * SIMILAR COSTS, WHETHER ASSERTED ON THE BASIS OF CONTRACT, TORT
42 * (INCLUDING NEGLIGENCE), BREACH OF WARRANTY, OR OTHERWISE.
43 *
44 *
45 * Author Date Comment
46 *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
47 * Howard Schlunder 06/12/05 Modified for 97J60 (from ENC28J60)
48 * Howard Schlunder 03/23/06 Updated for Advance Data Sheet
49 * Howard Schlunder 06/29/06 Changed MACON3_PHDRLEN to MACON3_PHDREN
50 * Howard Schlunder 09/13/06 Removed a lot of bits for
51 * preliminary data sheet, added RXAPDIS
52 ********************************************************************/
53  
54 #ifndef __ETH97J60_H
55 #define __ETH97J60_H
56 #include "GenericTypeDefs.h"
57  
58 typedef union {
59 BYTE v[7];
60 struct {
61 WORD ByteCount;
62 unsigned CollisionCount:4;
63 unsigned CRCError:1;
64 unsigned LengthCheckError:1;
65 unsigned LengthOutOfRange:1;
66 unsigned Done:1;
67 unsigned Multicast:1;
68 unsigned Broadcast:1;
69 unsigned PacketDefer:1;
70 unsigned ExcessiveDefer:1;
71 unsigned MaximumCollisions:1;
72 unsigned LateCollision:1;
73 unsigned Giant:1;
74 unsigned Underrun:1;
75 WORD BytesTransmittedOnWire;
76 unsigned ControlFrame:1;
77 unsigned PAUSEControlFrame:1;
78 unsigned BackpressureApplied:1;
79 unsigned VLANTaggedFrame:1;
80 unsigned Zeros:4;
81 } bits;
82 } TXSTATUS;
83  
84 typedef union {
85 BYTE v[4];
86 struct {
87 WORD ByteCount;
88 unsigned PreviouslyIgnored:1;
89 unsigned RXDCPreviouslySeen:1;
90 unsigned CarrierPreviouslySeen:1;
91 unsigned CodeViolation:1;
92 unsigned CRCError:1;
93 unsigned LengthCheckError:1;
94 unsigned LengthOutOfRange:1;
95 unsigned ReceiveOk:1;
96 unsigned Multicast:1;
97 unsigned Broadcast:1;
98 unsigned DribbleNibble:1;
99 unsigned ControlFrame:1;
100 unsigned PauseControlFrame:1;
101 unsigned UnsupportedOpcode:1;
102 unsigned VLANType:1;
103 unsigned Zero:1;
104 } bits;
105 } RXSTATUS;
106  
107  
108  
109 /******************************************************************************
110 * PHY Register Locations
111 ******************************************************************************/
112 #define PHCON1 0x00
113 #define PHSTAT1 0x01
114 #define PHCON2 0x10
115 #define PHSTAT2 0x11
116 #define PHIE 0x12
117 #define PHIR 0x13
118 #define PHLCON 0x14
119  
120  
121 typedef union {
122 WORD Val;
123 WORD_VAL VAL;
124  
125 // PHCON1 bits ----------
126 struct {
127 unsigned :8;
128 unsigned PDPXMD:1;
129 unsigned :7;
130 } PHCON1bits;
131  
132 // PHSTAT1 bits --------
133 struct {
134 unsigned :2;
135 unsigned LLSTAT:1;
136 unsigned :5;
137 unsigned :8;
138 } PHSTAT1bits;
139  
140 // PHCON2 bits ----------
141 struct {
142 unsigned :4;
143 unsigned RXAPDIS:1;
144 unsigned :3;
145 unsigned HDLDIS:1;
146 unsigned :5;
147 unsigned FRCLNK:1;
148 unsigned :1;
149 } PHCON2bits;
150  
151 // PHSTAT2 bits --------
152 struct {
153 unsigned :8;
154 unsigned :2;
155 unsigned LSTAT:1;
156 unsigned COLSTAT:1;
157 unsigned RXSTAT:1;
158 unsigned TXSTAT:1;
159 unsigned :2;
160 } PHSTAT2bits;
161  
162 // PHIE bits -----------
163 struct {
164 unsigned :1;
165 unsigned PGEIE:1;
166 unsigned :2;
167 unsigned PLNKIE:1;
168 unsigned :3;
169 unsigned :8;
170 } PHIEbits;
171  
172 // PHIR bits -----------
173 struct {
174 unsigned :2;
175 unsigned PGIF:1;
176 unsigned :1;
177 unsigned PLNKIF:1;
178 unsigned :3;
179 unsigned :8;
180 } PHIRbits;
181  
182 // PHLCON bits -------
183 struct {
184 unsigned :1;
185 unsigned STRCH:1;
186 unsigned LFRQ0:1;
187 unsigned LFRQ1:1;
188 unsigned LBCFG0:1;
189 unsigned LBCFG1:1;
190 unsigned LBCFG2:1;
191 unsigned LBCFG3:1;
192 unsigned LACFG0:1;
193 unsigned LACFG1:1;
194 unsigned LACFG2:1;
195 unsigned LACFG3:1;
196 unsigned :4;
197 } PHLCONbits;
198 struct {
199 unsigned :1;
200 unsigned STRCH:1;
201 unsigned LFRQ:2;
202 unsigned LBCFG:4;
203 unsigned LACFG:4;
204 unsigned :4;
205 } PHLCONbits2;
206 } PHYREG;
207  
208  
209 /******************************************************************************
210 * Individual Register Bits
211 ******************************************************************************/
212 // ETH/MAC/MII bits
213  
214 // EIE bits ----------
215 #define EIE_PKTIE (1<<6)
216 #define EIE_DMAIE (1<<5)
217 #define EIE_LINKIE (1<<4)
218 #define EIE_TXIE (1<<3)
219 #define EIE_TXERIE (1<<1)
220 #define EIE_RXERIE (1)
221  
222 // EIR bits ----------
223 #define EIR_PKTIF (1<<6)
224 #define EIR_DMAIF (1<<5)
225 #define EIR_LINKIF (1<<4)
226 #define EIR_TXIF (1<<3)
227 #define EIR_TXERIF (1<<1)
228 #define EIR_RXERIF (1)
229  
230 // ESTAT bits ---------
231 #define ESTAT_BUFER (1<<6)
232 #define ESTAT_RXBUSY (1<<2)
233 #define ESTAT_TXABRT (1<<1)
234 #define ESTAT_PHYRDY (1)
235  
236 // ECON2 bits --------
237 #define ECON2_AUTOINC (1<<7)
238 #define ECON2_PKTDEC (1<<6)
239 #define ECON2_ETHEN (1<<5)
240  
241 // ECON1 bits --------
242 #define ECON1_TXRST (1<<7)
243 #define ECON1_RXRST (1<<6)
244 #define ECON1_DMAST (1<<5)
245 #define ECON1_CSUMEN (1<<4)
246 #define ECON1_TXRTS (1<<3)
247 #define ECON1_RXEN (1<<2)
248  
249 // ERXFCON bits ------
250 #define ERXFCON_UCEN (1<<7)
251 #define ERXFCON_ANDOR (1<<6)
252 #define ERXFCON_CRCEN (1<<5)
253 #define ERXFCON_PMEN (1<<4)
254 #define ERXFCON_MPEN (1<<3)
255 #define ERXFCON_HTEN (1<<2)
256 #define ERXFCON_MCEN (1<<1)
257 #define ERXFCON_BCEN (1)
258  
259 // MACON1 bits --------
260 #define MACON1_TXPAUS (1<<3)
261 #define MACON1_RXPAUS (1<<2)
262 #define MACON1_PASSALL (1<<1)
263 #define MACON1_MARXEN (1)
264  
265 // MACON3 bits --------
266 #define MACON3_PADCFG2 (1<<7)
267 #define MACON3_PADCFG1 (1<<6)
268 #define MACON3_PADCFG0 (1<<5)
269 #define MACON3_TXCRCEN (1<<4)
270 #define MACON3_PHDREN (1<<3)
271 #define MACON3_HFRMEN (1<<2)
272 #define MACON3_FRMLNEN (1<<1)
273 #define MACON3_FULDPX (1)
274  
275 // MACON4 bits --------
276 #define MACON4_DEFER (1<<6)
277  
278 // MICMD bits ---------
279 #define MICMD_MIISCAN (1<<1)
280 #define MICMD_MIIRD (1)
281  
282 // MISTAT bits --------
283 #define MISTAT_NVALID (1<<2)
284 #define MISTAT_SCAN (1<<1)
285 #define MISTAT_BUSY (1)
286  
287 // EFLOCON bits -----
288 #define EFLOCON_FCEN1 (1<<1)
289 #define EFLOCON_FCEN0 (1)
290  
291  
292  
293 // PHY bits
294  
295 // PHCON1 bits ----------
296 #define PHCON1_PDPXMD (1ul<<8)
297  
298 // PHSTAT1 bits --------
299 #define PHSTAT1_LLSTAT (1ul<<2)
300  
301 // PHCON2 bits ----------
302 #define PHCON2_FRCLNK (1ul<<14)
303 #define PHCON2_HDLDIS (1ul<<8)
304 #define PHCON2_RXAPDIS (1ul<<4)
305  
306 // PHSTAT2 bits --------
307 #define PHSTAT2_TXSTAT (1ul<<13)
308 #define PHSTAT2_RXSTAT (1ul<<12)
309 #define PHSTAT2_COLSTAT (1ul<<11)
310 #define PHSTAT2_LSTAT (1ul<<10)
311  
312 // PHIE bits -----------
313 #define PHIE_PLNKIE (1ul<<4)
314 #define PHIE_PGEIE (1ul<<1)
315  
316 // PHIR bits -----------
317 #define PHIR_PLNKIF (1ul<<4)
318 #define PHIR_PGIF (1ul<<2)
319  
320 // PHLCON bits -------
321 #define PHLCON_LACFG3 (1ul<<11)
322 #define PHLCON_LACFG2 (1ul<<10)
323 #define PHLCON_LACFG1 (1ul<<9)
324 #define PHLCON_LACFG0 (1ul<<8)
325 #define PHLCON_LBCFG3 (1ul<<7)
326 #define PHLCON_LBCFG2 (1ul<<6)
327 #define PHLCON_LBCFG1 (1ul<<5)
328 #define PHLCON_LBCFG0 (1ul<<4)
329 #define PHLCON_LFRQ1 (1ul<<3)
330 #define PHLCON_LFRQ0 (1ul<<2)
331 #define PHLCON_STRCH (1ul<<1)
332  
333 #endif
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